ed8e4d8d39
Working linuxcnc lathe config with 2 ms cycle time
Hakan Bastedt2024-04-07 21:53:25 +02:00
a829b0c6e2
Standalone unix port of step generator, also stm32 arduino
Hakan Bastedt2024-04-07 21:51:36 +02:00
ab1a306d86
Works really nice now. 20 usecs base period => 50 kHz, 25 kHz pulse freq.
Hakan Bastedt2024-04-07 21:45:53 +02:00
544dd5ed85
I works. Use 4.19-rt kernel Ethernet Intel I210 controller ethtool -C enp1s0 rx-usecs 0 tx-usecs 0 2 ms loop time in linuxcnc .ini and .xml and code baseTimer period can be adjusted startTime for baseTimer can also be adjusted.
Hakan Bastedt2024-04-05 18:30:33 +02:00
2df0a0980c
Stepgen3 is driven by HardwareTimer, in a way that resembles EtherCAT setup. Seems to actually work.
Hakan Bastedt2024-03-22 22:38:16 +01:00
6383d6de89
Working test-program using user LEDs and delays
Hakan Bastedt2024-03-22 21:20:31 +01:00
7bff3f3789
linuxcnc stepgen is now in StepGen3. Compiles
Hakan Bastedt2024-03-22 17:31:21 +01:00
23fe81afbe
Factored Stepgen2, StepGen3 is a copy of Stepgen2
Hakan Bastedt2024-03-21 16:45:59 +01:00
fa34d81e41
Factored Stepgen2, StepGen3 is a copy of Stepgen2
Hakan Bastedt2024-03-21 16:45:46 +01:00
30a9f10c7b
Well it works, network-wise. But there are those extra peaks that have been since the start. Let's see if I can remove them. Welcome StepGen3
Hakan Bastedt2024-03-21 16:28:55 +01:00
8f26a10224
It works. I hate RealTek. Even with the r8618_dkms driver it doesn't work. I bought a Intel network card, set irq coalesce rx-usecs and tx-usecs to 0. Now it works works WORKS. No lost packages, no delayed packages. I hate RealTek
Hakan Bastedt2024-03-20 17:06:24 +01:00
d4fed6cfe8
Yes it works now. Made another implementation of the pulse IRQ and all that. We'll see if I keep this or go back to the older. It is IMPORTANT, REQUIRED to use a 4.9 linux kernel for it to work. There are obviously bugs in the RealTek network drivers R8168/R8169 in 5+ kernels. All this work could have been avoided with a 4.9 kernel.
Hakan Bastedt2024-03-17 22:04:52 +01:00
27475eaecd
Seems to actually work, but I have seen that before, so testing time
Hakan Bastedt2024-03-14 10:15:23 +01:00
c0d2bfcf62
doc update on stepgen problem and solution
Hakan Bastedt2024-02-12 18:37:16 +01:00
f4a15afa8a
a cycle's pwm train maight have been too long and run into the start of next cycle's pwm train. That's gone now and it seems to work. A more brilliant solution is needed for this.
Hakan Bastedt2024-02-11 19:55:40 +01:00
c04ac0e74b
Consistently get SM2 event now. Must check directly in irq. DIG_PROCESS modified to check this ALevent copy
Hakan Bastedt2024-02-09 22:58:28 +01:00
6d18c2cb3f
Clear ALevents for DC_sync0 and SM3 might have solved the uneven pulse train. Looking better now.
Hakan Bastedt2024-02-09 17:28:18 +01:00
d0433b29cf
cleanup and removing StepGen from active code
Hakan Bastedt2024-02-08 21:33:31 +01:00
Hakan Bastedt
Håkan BåstedtandGitHub
