Hakan Bastedt
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fef934b103
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wip
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2024-03-10 01:03:50 +01:00 |
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Hakan Bastedt
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30dc44d5e6
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Direction output to dirPin.
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2024-02-16 11:45:06 +01:00 |
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Hakan Bastedt
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2b2be4f63d
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Going for test in the lathe
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2024-02-13 10:49:57 +01:00 |
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Hakan Bastedt
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f4a15afa8a
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a cycle's pwm train maight have been too long and run into the start of next cycle's pwm train. That's gone now and it seems to work.
A more brilliant solution is needed for this.
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2024-02-11 19:56:16 +01:00 |
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Hakan Bastedt
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c04ac0e74b
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Consistently get SM2 event now. Must check directly in irq. DIG_PROCESS modified to check this ALevent copy
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2024-02-09 22:58:28 +01:00 |
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Hakan Bastedt
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6d18c2cb3f
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Clear ALevents for DC_sync0 and SM3 might have solved the uneven pulse train. Looking better now.
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2024-02-09 17:28:18 +01:00 |
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Hakan Bastedt
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d0433b29cf
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cleanup and removing StepGen from active code
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2024-02-08 21:33:31 +01:00 |
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Hakan Bastedt
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fe3de876fa
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Class StepGen2 done after Stepgen.odb
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2024-02-08 21:28:48 +01:00 |
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Hakan Bastedt
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43854ca4d0
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wip
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2024-02-05 21:22:23 +01:00 |
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Hakan Bastedt
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2b2704bb17
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Added timer2 for proper start point
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2024-02-02 21:43:58 +01:00 |
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Hakan Bastedt
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0384646972
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wip
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2024-02-02 15:26:01 +01:00 |
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Hakan Bastedt
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133df5662d
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wip, before timer stuff
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2024-02-02 12:09:49 +01:00 |
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Hakan Bastedt
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d1eb1d9a40
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logic might be there
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2024-02-01 20:30:02 +01:00 |
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