Hakan Bastedt
|
fa34d81e41
|
Factored Stepgen2, StepGen3 is a copy of Stepgen2
|
2024-03-21 16:45:46 +01:00 |
|
Hakan Bastedt
|
30a9f10c7b
|
Well it works, network-wise. But there are those extra peaks that have been since the start. Let's see if I can remove them. Welcome StepGen3
|
2024-03-21 16:28:55 +01:00 |
|
Hakan Bastedt
|
8f26a10224
|
It works. I hate RealTek. Even with the r8618_dkms driver it doesn't work. I bought a Intel network card, set irq coalesce rx-usecs and tx-usecs to 0. Now it works works WORKS. No lost packages, no delayed packages. I hate RealTek
|
2024-03-20 17:06:24 +01:00 |
|
Hakan Bastedt
|
d4fed6cfe8
|
Yes it works now. Made another implementation of the pulse IRQ and all that. We'll see if I keep this or go back to the older. It is IMPORTANT, REQUIRED to use a 4.9 linux kernel for it to work. There are obviously bugs in the RealTek network drivers R8168/R8169 in 5+ kernels. All this work could have been avoided with a 4.9 kernel.
|
2024-03-17 22:04:52 +01:00 |
|
Hakan Bastedt
|
71ae242fc4
|
Fixed bug in extend32to64:extendTime()
|
2024-03-13 23:33:25 +01:00 |
|
Hakan Bastedt
|
fef934b103
|
wip
|
2024-03-10 01:03:50 +01:00 |
|
Hakan Bastedt
|
30dc44d5e6
|
Direction output to dirPin.
|
2024-02-16 11:45:06 +01:00 |
|
Hakan Bastedt
|
2b2be4f63d
|
Going for test in the lathe
|
2024-02-13 10:49:57 +01:00 |
|
Hakan Bastedt
|
f4a15afa8a
|
a cycle's pwm train maight have been too long and run into the start of next cycle's pwm train. That's gone now and it seems to work.
A more brilliant solution is needed for this.
|
2024-02-11 19:56:16 +01:00 |
|
Hakan Bastedt
|
c04ac0e74b
|
Consistently get SM2 event now. Must check directly in irq. DIG_PROCESS modified to check this ALevent copy
|
2024-02-09 22:58:28 +01:00 |
|
Hakan Bastedt
|
6d18c2cb3f
|
Clear ALevents for DC_sync0 and SM3 might have solved the uneven pulse train. Looking better now.
|
2024-02-09 17:28:18 +01:00 |
|
Hakan Bastedt
|
d0433b29cf
|
cleanup and removing StepGen from active code
|
2024-02-08 21:33:31 +01:00 |
|
Hakan Bastedt
|
fe3de876fa
|
Class StepGen2 done after Stepgen.odb
|
2024-02-08 21:28:48 +01:00 |
|
Hakan Bastedt
|
43854ca4d0
|
wip
|
2024-02-05 21:22:23 +01:00 |
|
Hakan Bastedt
|
2b2704bb17
|
Added timer2 for proper start point
|
2024-02-02 21:43:58 +01:00 |
|
Hakan Bastedt
|
0384646972
|
wip
|
2024-02-02 15:26:01 +01:00 |
|
Hakan Bastedt
|
133df5662d
|
wip, before timer stuff
|
2024-02-02 12:09:49 +01:00 |
|
Hakan Bastedt
|
d1eb1d9a40
|
logic might be there
|
2024-02-01 20:30:02 +01:00 |
|