653 lines
35 KiB
C++
Executable File
653 lines
35 KiB
C++
Executable File
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#ifndef __Stm32F4_Encoder_H__
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#define __Stm32F4_Encoder_H__
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#include <Arduino.h>
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#define GPIO_Speed_50MHz 0x02 /*!< Fast speed */
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// #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
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#define GPIO_Mode_OUT 0x01
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// #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
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// #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
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// #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
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#define GPIO_PuPd_NOPULL 0x00
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#define GPIO_Mode_AF 0x02
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#define GPIO_OType_PP 0x00
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#define GPIO_PuPd_NOPULL 0x00
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#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
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#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
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#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
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#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
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#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
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#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
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#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
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#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
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#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
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#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
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#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
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#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
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#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
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#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
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#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
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#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
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#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
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typedef struct TIM_TimeBaseInitTypeDef
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{
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uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
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This parameter can be a value of @ref TIM_Counter_Mode */
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uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
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Auto-Reload Register at the next update event.
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This parameter must be a number between 0x0000 and 0xFFFF. */
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uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
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This parameter can be a value of @ref TIM_Clock_Division_CKD */
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uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
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reaches zero, an update event is generated and counting restarts
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from the RCR value (N).
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This means in PWM mode that (N+1) corresponds to:
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- the number of PWM periods in edge-aligned mode
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- the number of half PWM period in center-aligned mode
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This parameter must be a number between 0x00 and 0xFF.
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@note This parameter is valid only for TIM1 and TIM8. */
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} TIM_TimeBaseInitTypeDef;
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typedef struct
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{
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uint16_t setcount;
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} encoder;
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typedef struct
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{
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uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
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This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
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This parameter can be a value of @ref TIM_Output_Compare_State */
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uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
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This parameter can be a value of @ref TIM_Output_Compare_N_State
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@note This parameter is valid only for TIM1 and TIM8. */
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uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
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This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
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This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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@note This parameter is valid only for TIM1 and TIM8. */
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uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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@note This parameter is valid only for TIM1 and TIM8. */
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uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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@note This parameter is valid only for TIM1 and TIM8. */
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} TIM_OCInitTypeDef;
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typedef struct
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{
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uint16_t TIM_Channel; /*!< Specifies the TIM channel.
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This parameter can be a value of @ref TIM_Channel */
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uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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uint16_t TIM_ICSelection; /*!< Specifies the input.
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This parameter can be a value of @ref TIM_Input_Capture_Selection */
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uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
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This parameter can be a number between 0x0 and 0xF */
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} TIM_ICInitTypeDef;
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typedef struct
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{
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uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
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This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
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uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
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This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
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uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
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This parameter can be a value of @ref TIM_Lock_level */
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uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
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switching-on of the outputs.
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This parameter can be a number between 0x00 and 0xFF */
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uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
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This parameter can be a value of @ref TIM_Break_Input_enable_disable */
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uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
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This parameter can be a value of @ref TIM_Break_Polarity */
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uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
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This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
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} TIM_BDTRInitTypeDef;
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#define GPIO_PinSource0 ((uint8_t)0x00)
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#define GPIO_PinSource1 ((uint8_t)0x01)
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#define GPIO_PinSource2 ((uint8_t)0x02)
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#define GPIO_PinSource3 ((uint8_t)0x03)
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#define GPIO_PinSource4 ((uint8_t)0x04)
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#define GPIO_PinSource5 ((uint8_t)0x05)
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#define GPIO_PinSource6 ((uint8_t)0x06)
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#define GPIO_PinSource7 ((uint8_t)0x07)
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#define GPIO_PinSource8 ((uint8_t)0x08)
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#define GPIO_PinSource9 ((uint8_t)0x09)
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#define GPIO_PinSource10 ((uint8_t)0x0A)
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#define GPIO_PinSource11 ((uint8_t)0x0B)
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#define GPIO_PinSource12 ((uint8_t)0x0C)
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#define GPIO_PinSource13 ((uint8_t)0x0D)
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#define GPIO_PinSource14 ((uint8_t)0x0E)
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#define GPIO_PinSource15 ((uint8_t)0x0F)
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#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
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#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
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#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
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#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
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#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
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#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
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// #define TIM4 ((TIM_TypeDef *)TIM4_BASE)
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// #define TIM8 ((TIM_TypeDef *)TIM8_BASE)
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#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
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#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
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#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
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// #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
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// #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
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#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM6) || \
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((PERIPH) == TIM7) || \
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((PERIPH) == TIM8) || \
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((PERIPH) == TIM9) || \
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((PERIPH) == TIM10) || \
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((PERIPH) == TIM11) || \
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((PERIPH) == TIM12) || \
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(((PERIPH) == TIM13) || \
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((PERIPH) == TIM14)))
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#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM8) || \
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((PERIPH) == TIM9) || \
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((PERIPH) == TIM10) || \
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((PERIPH) == TIM11) || \
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((PERIPH) == TIM12) || \
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((PERIPH) == TIM13) || \
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((PERIPH) == TIM14))
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#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM8) || \
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((PERIPH) == TIM9) || \
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((PERIPH) == TIM12))
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#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM8))
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#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM8))
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#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM6) || \
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((PERIPH) == TIM7) || \
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((PERIPH) == TIM8))
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#define IS_TIM_LIST6_PERIPH(TIMx) (((TIMx) == TIM2) || \
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((TIMx) == TIM5) || \
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((TIMx) == TIM11))
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#define TIM_OCMode_Timing ((uint16_t)0x0000)
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#define TIM_OCMode_Active ((uint16_t)0x0010)
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#define TIM_OCMode_Inactive ((uint16_t)0x0020)
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#define TIM_OCMode_Toggle ((uint16_t)0x0030)
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#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
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#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
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//#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
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// ((MODE) == TIM_OCMode_Active) || \
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// ((MODE) == TIM_OCMode_Inactive) || \
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// ((MODE) == TIM_OCMode_Toggle)|| \
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// ((MODE) == TIM_OCMode_PWM1) || \
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// ((MODE) == TIM_OCMode_PWM2))
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#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
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((MODE) == TIM_OCMode_Active) || \
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((MODE) == TIM_OCMode_Inactive) || \
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((MODE) == TIM_OCMode_Toggle) || \
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((MODE) == TIM_OCMode_PWM1) || \
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((MODE) == TIM_OCMode_PWM2) || \
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((MODE) == TIM_ForcedAction_Active) || \
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((MODE) == TIM_ForcedAction_InActive))
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#define TIM_OPMode_Single ((uint16_t)0x0008)
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#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
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//#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
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// ((MODE) == TIM_OPMode_Repetitive))
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#define TIM_Channel_1 ((uint16_t)0x0000)
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#define TIM_Channel_2 ((uint16_t)0x0004)
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#define TIM_Channel_3 ((uint16_t)0x0008)
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#define TIM_Channel_4 ((uint16_t)0x000C)
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#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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((CHANNEL) == TIM_Channel_2) || \
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((CHANNEL) == TIM_Channel_3) || \
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((CHANNEL) == TIM_Channel_4))
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#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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((CHANNEL) == TIM_Channel_2))
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#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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((CHANNEL) == TIM_Channel_2) || \
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((CHANNEL) == TIM_Channel_3))
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#define TIM_CKD_DIV1 ((uint16_t)0x0000)
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#define TIM_CKD_DIV2 ((uint16_t)0x0100)
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#define TIM_CKD_DIV4 ((uint16_t)0x0200)
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#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
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((DIV) == TIM_CKD_DIV2) || \
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((DIV) == TIM_CKD_DIV4))
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#define TIM_CounterMode_Up ((uint16_t)0x0000)
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#define TIM_CounterMode_Down ((uint16_t)0x0010)
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#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
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#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
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#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
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//#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
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// ((MODE) == TIM_CounterMode_Down) || \
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// ((MODE) == TIM_CounterMode_CenterAligned1) || \
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// ((MODE) == TIM_CounterMode_CenterAligned2) || \
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// ((MODE) == TIM_CounterMode_CenterAligned3))
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#define TIM_OCPolarity_High ((uint16_t)0x0000)
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#define TIM_OCPolarity_Low ((uint16_t)0x0002)
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//#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
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// ((POLARITY) == TIM_OCPolarity_Low))
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#define TIM_OCNPolarity_High ((uint16_t)0x0000)
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#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
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//#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
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// ((POLARITY) == TIM_OCNPolarity_Low))
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#define TIM_OutputState_Disable ((uint16_t)0x0000)
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#define TIM_OutputState_Enable ((uint16_t)0x0001)
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#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
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((STATE) == TIM_OutputState_Enable))
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#define TIM_OutputNState_Disable ((uint16_t)0x0000)
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#define TIM_OutputNState_Enable ((uint16_t)0x0004)
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#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
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((STATE) == TIM_OutputNState_Enable))
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#define TIM_CCx_Enable ((uint16_t)0x0001)
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#define TIM_CCx_Disable ((uint16_t)0x0000)
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#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
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((CCX) == TIM_CCx_Disable))
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#define TIM_CCxN_Enable ((uint16_t)0x0004)
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#define TIM_CCxN_Disable ((uint16_t)0x0000)
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#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
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((CCXN) == TIM_CCxN_Disable))
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#define TIM_Break_Enable ((uint16_t)0x1000)
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#define TIM_Break_Disable ((uint16_t)0x0000)
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//#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
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// ((STATE) == TIM_Break_Disable))
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#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
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#define TIM_BreakPolarity_High ((uint16_t)0x2000)
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//#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
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// ((POLARITY) == TIM_BreakPolarity_High))
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#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
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#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
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//#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
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// ((STATE) == TIM_AutomaticOutput_Disable))
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#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
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#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
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#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
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#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
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//#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
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// ((LEVEL) == TIM_LOCKLevel_1) || \
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// ((LEVEL) == TIM_LOCKLevel_2) || \
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// ((LEVEL) == TIM_LOCKLevel_3))
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#define TIM_OSSIState_Enable ((uint16_t)0x0400)
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#define TIM_OSSIState_Disable ((uint16_t)0x0000)
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//#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
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// ((STATE) == TIM_OSSIState_Disable))
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#define TIM_OSSRState_Enable ((uint16_t)0x0800)
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#define TIM_OSSRState_Disable ((uint16_t)0x0000)
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//#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
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// ((STATE) == TIM_OSSRState_Disable))
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#define TIM_OCIdleState_Set ((uint16_t)0x0100)
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#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
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//#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
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// ((STATE) == TIM_OCIdleState_Reset))
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//
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#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
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#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
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//#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
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// ((STATE) == TIM_OCNIdleState_Reset))
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#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
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#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
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#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
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//#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
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// ((POLARITY) == TIM_ICPolarity_Falling)|| \
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// ((POLARITY) == TIM_ICPolarity_BothEdge))
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#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
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connected to IC1, IC2, IC3 or IC4, respectively */
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#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be \
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connected to IC2, IC1, IC4 or IC3, respectively. */
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#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
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//#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
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// ((SELECTION) == TIM_ICSelection_IndirectTI) || \
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// ((SELECTION) == TIM_ICSelection_TRC))
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// #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
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// #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
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// #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
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// #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
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// #define IS_TIM_IC_PRESCALER(PRESCALER) ( ((PRESCALER) == TIM_ICPSC_DIV1) || \
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// ((PRESCALER) == TIM_ICPSC_DIV2) || \
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// ((PRESCALER) == TIM_ICPSC_DIV4) || \
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// ((PRESCALER) == TIM_ICPSC_DIV8))
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#define TIM_IT_Update ((uint16_t)0x0001)
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// #define TIM_IT_CC1 ((uint16_t)0x0002)
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// #define TIM_IT_CC2 ((uint16_t)0x0004)
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// #define TIM_IT_CC3 ((uint16_t)0x0008)
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// #define TIM_IT_CC4 ((uint16_t)0x0010)
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// #define TIM_IT_COM ((uint16_t)0x0020)
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#define TIM_IT_Trigger ((uint16_t)0x0040)
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#define TIM_IT_Break ((uint16_t)0x0080)
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#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
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#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
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((IT) == TIM_IT_CC1) || \
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((IT) == TIM_IT_CC2) || \
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((IT) == TIM_IT_CC3) || \
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((IT) == TIM_IT_CC4) || \
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((IT) == TIM_IT_COM) || \
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((IT) == TIM_IT_Trigger) || \
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((IT) == TIM_IT_Break))
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// #define TIM_DMABase_CR1 ((uint16_t)0x0000)
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// #define TIM_DMABase_CR2 ((uint16_t)0x0001)
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// #define TIM_DMABase_SMCR ((uint16_t)0x0002)
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// #define TIM_DMABase_DIER ((uint16_t)0x0003)
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// #define TIM_DMABase_SR ((uint16_t)0x0004)
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// #define TIM_DMABase_EGR ((uint16_t)0x0005)
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// #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
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// #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
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// #define TIM_DMABase_CCER ((uint16_t)0x0008)
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// #define TIM_DMABase_CNT ((uint16_t)0x0009)
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// #define TIM_DMABase_PSC ((uint16_t)0x000A)
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// #define TIM_DMABase_ARR ((uint16_t)0x000B)
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// #define TIM_DMABase_RCR ((uint16_t)0x000C)
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// #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
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// #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
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// #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
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// #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
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// #define TIM_DMABase_BDTR ((uint16_t)0x0011)
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// #define TIM_DMABase_DCR ((uint16_t)0x0012)
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// #define TIM_DMABase_OR ((uint16_t)0x0013)
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// #define IS_TIM_DMA_BASE(BASE) ( ((BASE) == TIM_DMABase_CR1) || \
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// ((BASE) == TIM_DMABase_CR2) || \
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// ((BASE) == TIM_DMABase_SMCR) || \
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// ((BASE) == TIM_DMABase_DIER) || \
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// ((BASE) == TIM_DMABase_SR) || \
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// ((BASE) == TIM_DMABase_EGR) || \
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// ((BASE) == TIM_DMABase_CCMR1) || \
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// ((BASE) == TIM_DMABase_CCMR2) || \
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// ((BASE) == TIM_DMABase_CCER) || \
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// ((BASE) == TIM_DMABase_CNT) || \
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// ((BASE) == TIM_DMABase_PSC) || \
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// ((BASE) == TIM_DMABase_ARR) || \
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// ((BASE) == TIM_DMABase_RCR) || \
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// ((BASE) == TIM_DMABase_CCR1) || \
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// ((BASE) == TIM_DMABase_CCR2) || \
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// ((BASE) == TIM_DMABase_CCR3) || \
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// ((BASE) == TIM_DMABase_CCR4) || \
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// ((BASE) == TIM_DMABase_BDTR) || \
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// ((BASE) == TIM_DMABase_DCR) || \
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// ((BASE) == TIM_DMABase_OR))
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// #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
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// #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
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// #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
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// #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
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// #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
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// #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
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// #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
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// #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
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// #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
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// #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
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// #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
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// #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
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// #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
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// #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
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// #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
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// #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
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// #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
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// #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
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// #define IS_TIM_DMA_LENGTH(LENGTH) ( ((LENGTH) == TIM_DMABurstLength_1Transfer) || \
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// ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
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// ((LENGTH) == TIM_DMABurstLength_18Transfers))
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// #define TIM_DMA_Update ((uint16_t)0x0100)
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// #define TIM_DMA_CC1 ((uint16_t)0x0200)
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// #define TIM_DMA_CC2 ((uint16_t)0x0400)
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// #define TIM_DMA_CC3 ((uint16_t)0x0800)
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// #define TIM_DMA_CC4 ((uint16_t)0x1000)
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// #define TIM_DMA_COM ((uint16_t)0x2000)
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// #define TIM_DMA_Trigger ((uint16_t)0x4000)
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// #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
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#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
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#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
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|
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
|
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
|
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
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|
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
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|
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
|
|
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
|
|
|
|
// #define TIM_TS_ITR0 ((uint16_t)0x0000)
|
|
// #define TIM_TS_ITR1 ((uint16_t)0x0010)
|
|
// #define TIM_TS_ITR2 ((uint16_t)0x0020)
|
|
// #define TIM_TS_ITR3 ((uint16_t)0x0030)
|
|
// #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
|
// #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
|
// #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
|
// #define TIM_TS_ETRF ((uint16_t)0x0070)
|
|
// #def ine IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
|
// ((SELECTION) == TIM_TS_ITR1) || \
|
|
// ((SELECTION) == TIM_TS_ITR2) || \
|
|
// ((SELECTION) == TIM_TS_ITR3) || \
|
|
// ((SELECTION) == TIM_TS_TI1F_ED) || \
|
|
// ((SELECTION) == TIM_TS_TI1FP1) || \
|
|
// ((SELECTION) == TIM_TS_TI2FP2) || \
|
|
// ((SELECTION) == TIM_TS_ETRF))
|
|
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
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|
((SELECTION) == TIM_TS_ITR1) || \
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|
((SELECTION) == TIM_TS_ITR2) || \
|
|
((SELECTION) == TIM_TS_ITR3))
|
|
|
|
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
|
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
|
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
|
|
|
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
|
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
|
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
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|
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
|
|
|
|
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
|
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
|
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
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|
((RELOAD) == TIM_PSCReloadMode_Immediate))
|
|
|
|
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
|
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
|
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
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|
((ACTION) == TIM_ForcedAction_InActive))
|
|
|
|
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
|
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
|
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
|
//#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
|
|
// ((MODE) == TIM_EncoderMode_TI2) || \
|
|
// ((MODE) == TIM_EncoderMode_TI12))
|
|
|
|
// #define TIM_EventSource_Update ((uint16_t)0x0001)
|
|
// #define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
|
// #define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
|
// #define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
|
// #define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
|
// #define TIM_EventSource_COM ((uint16_t)0x0020)
|
|
// #define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
|
// #define TIM_EventSource_Break ((uint16_t)0x0080)
|
|
// #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
|
|
|
|
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow \
|
|
or the setting of UG bit, or an update generation \
|
|
through the slave mode controller. */
|
|
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
|
|
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
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|
((SOURCE) == TIM_UpdateSource_Regular))
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|
|
|
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
|
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
|
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
|
|
((STATE) == TIM_OCPreload_Disable))
|
|
|
|
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
|
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
|
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
|
|
((STATE) == TIM_OCFast_Disable))
|
|
|
|
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
|
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
|
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
|
|
((STATE) == TIM_OCClear_Disable))
|
|
|
|
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
|
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
|
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
|
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
|
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
|
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
|
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
|
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
|
//#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
|
|
// ((SOURCE) == TIM_TRGOSource_Enable) || \
|
|
// ((SOURCE) == TIM_TRGOSource_Update) || \
|
|
// ((SOURCE) == TIM_TRGOSource_OC1) || \
|
|
// ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
|
|
// ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
|
|
// ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
|
|
// ((SOURCE) == TIM_TRGOSource_OC4Ref))
|
|
|
|
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
|
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
|
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
|
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
|
//#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
|
|
// ((MODE) == TIM_SlaveMode_Gated) || \
|
|
// ((MODE) == TIM_SlaveMode_Trigger) || \
|
|
// ((MODE) == TIM_SlaveMode_External1))
|
|
|
|
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
|
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
|
//#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
|
|
// ((STATE) == TIM_MasterSlaveMode_Disable))
|
|
|
|
#define TIM2_TIM8_TRGO ((uint16_t)0x0000)
|
|
#define TIM2_ETH_PTP ((uint16_t)0x0400)
|
|
#define TIM2_USBFS_SOF ((uint16_t)0x0800)
|
|
#define TIM2_USBHS_SOF ((uint16_t)0x0C00)
|
|
|
|
#define TIM5_GPIO ((uint16_t)0x0000)
|
|
#define TIM5_LSI ((uint16_t)0x0040)
|
|
#define TIM5_LSE ((uint16_t)0x0080)
|
|
#define TIM5_RTC ((uint16_t)0x00C0)
|
|
|
|
#define TIM11_GPIO ((uint16_t)0x0000)
|
|
#define TIM11_HSE ((uint16_t)0x0002)
|
|
|
|
class Encoder
|
|
{
|
|
private:
|
|
int _pin;
|
|
|
|
public:
|
|
TIM_TypeDef *tim_base;
|
|
Encoder();
|
|
void SetCount(int64_t Counter);
|
|
uint16_t GetCount();
|
|
};
|
|
|
|
void encoder_config();
|
|
void encoder2_config(); // Experimental
|
|
void GpioConfigPortA(GPIO_TypeDef *GPIOx);
|
|
void GpioConfigPortC(GPIO_TypeDef *GPIOx);
|
|
void GpioConfigPortD(GPIO_TypeDef *GPIOx);
|
|
void TIM_EncoderInterConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
|
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
|
|
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
|
|
#endif
|